Field of Invention
The present invention relates to a flyback converter, a primary side control circuit therein, and a control method thereof; particularly, it relates to such a flyback converter operating by synchronous rectification with a proper transient protection, and a primary side control circuit therein and a control method thereof.
Description of Related Art
FIGS. 1A-1C show schematic diagrams of a conventional flyback converter 100 with synchronous rectification, signal waveforms showing a synchronous rectification mechanism, and signal waveforms showing a phase-locked loop (PLL) protection mechanism, respectively. As shown in FIG. 1A, a rectifier circuit 101 rectifies an alternating current (AC) voltage Vac to generate an input voltage Vin. The rectifier circuit 101 is for example a bridge rectifier circuit. A transformer circuit 102 of the flyback converter 100 receives the input voltage Vin, and converts it to the output voltage Vout. The flyback converter 100 includes the aforementioned transformer circuit 102, a power switch circuit 103, an opto-coupler circuit 104, a primary side control circuit 105, a current sense circuit 106, a synchronous rectification (SR) control circuit 107, and an SR switch circuit 108. The primary side control circuit 105 generates an operation signal GATE according to a current sense signal CS generated by the current sense circuit 106 and a feedback signal COMP generated by the opto-coupler circuit 104; the operation signal GATE controls a power switch SW of the power switch circuit 103 to convert the input voltage Vin to the output voltage Vout. The transformer circuit 102 includes a primary winding W1 and a secondary winding W2. The secondary winding W2 is electrically connected to a ground level GND, and the primary winding W1 is electrically connected to a reference level REF. The current sense circuit 106 generates the current sense signal CS according to a power switch current flowing through the power switch SW of the power switch circuit 103.
FIG. 1B shows a condition that the flyback converter 100 operating with a voltage-second balance mechanism is in a steady state. “Steady state” means that the output voltage Vout is stably regulated at a target voltage. In the steady state, an average of an inductor voltage VLm across an inductor Lm in the transformer circuit 102 is zero during a cycle period. That is, the product of voltage and time during the period when the power switch SW is ON, i.e., a product of a voltage Vin′ of the inductor voltage VLm and an ON time period tON, is equal to the product of voltage and time during the period when the power switch SW is OFF, i.e., a product of a voltage nVout′ of the inductor voltage VLm and an OFF time period tOFF, which is the “voltage-second balance”.
In order to turn ON and OFF the SR power switch SWsr in the SR switch circuit at correct timings, an internal capacitor Ct is provided in the SR control circuit 107, which is charged and discharged according to the switching timings of the operation signal GATE. More specifically, a voltage Vct of an internal capacitor Ct is controlled to follow an inductor current ILm flowing through the inductor Lm of the transformer circuit 102. As shown in FIG. 1C, when the operation signal GATE is at a high level, the power switch SW is turned ON, whereas the SR power switch SWsr in the SR switch circuit 108 is turned OFF, so there is a voltage difference between the drain and source of the SR power switch SWsr and the drain voltage Vdsr of the power switch SWsr is high, and thus the internal capacitor Ct is charged. When the operation signal GATE is at a low level, the primary side power switch SW is turned OFF, but the current flowing through the inductor Lm is not zero, and thus it transfers energy to the secondary winding W2, and the parasitic diode Dsr in the SR switch circuit 108 is turned ON, and the drain voltage Vdsr is low. When the SR control circuit 107 detects that the drain voltage Vdsr switches from the high level to the low level, the SR control circuit 107 turns ON the SR power switch SWsr, and the internal capacitor Ct is discharged. When the capacitor voltage Vct decreases to 0V, the SR control circuit 107 turns OFF the SR power switch SWsr, whereby a synchronous rectification function is achieved, i.e., the period that the secondary side is conductive is synchronous with the period that the primary side is not conductive. The components in the SR control circuit 107 which control the charging and discharging currents of the internal capacitor Ct and the components in the SR control circuit 107 which generate the switch control signal for controlling the SR power switch SWsr are omitted for simplicity of the drawing.
The voltage-second balance mechanism is only achieved at the steady state. When the flyback converter 100 operates in a transient state, such as during a transient period wherein the frequency is increased, the flyback converter 100 is not operating under the voltage-second balance mechanism. In this case, the flyback converter 100 operates in a continuous conduction mode (CCM), wherein the internal capacitor Ct may not be discharged to 0V before the operation signal GATE switches to the high level, such that the SR control circuit 107 may not turn OFF the SR power switch SWsr in time. There is a very high risk that the primary side power switch SW and the SR power switch SWsr may be both conductive at the same time to cause a system crash.
To avoid the system crash, a phase-locked loop (PLL) protection mechanism is adopted in the secondary side SR control circuit 107 to limit a maximum ON time the SR power switch SWsr. Please refer to FIG. 1C. The PLL protection mechanism detects the drain voltage Vdsr of the SR power switch SWsr to obtain a previous cycle period ts_pri[n−1]. In the next (i.e., present) cycle period ts_pri[n], the SR control circuit 107 counts time from the beginning of the cycle period. When the time count reaches the previous cycle period ts_pri[n−1] minus a predetermined dead time tdead (i.e., the period ts_sec[n]), and if the internal capacitor Ct is not discharged to 0V yet, the SR control circuit 107 forces the SR power switch SWsr to turn OFF, so as to ensure that the flyback converter 100 operates safely from the system crash.
Obviously, for safety, the dead time tdead can not be set too short. However, if the dead time tdead is set too long, the SR power switch SWsr will be turned OFF too early and the flyback converter 100 will have a low efficiency. Hence, the stability and the efficiency of the flyback converter 100 become a trade-off. In addition, even if the dead time is set to an optimum value, it still does not completely solve the problem. When the flyback converter 100 operates in a transient period wherein the frequency is increased, i.e., the operation frequency of the operation signal GATE keeps increasing, the present cycle period ts_pri[n] may be shorter than the previous switching period ts_pri[n−1] minus the predetermined dead time tdead, i.e.,ts_pri[n]<ts_pri[n−1]−tdead=ts_sec[n], and under such circumstance, the PLL protection mechanism fails to protect the system from crash.
In view of the above, the present invention proposes a flyback converter operating by synchronous rectification with a proper transient protection, a primary side control circuit therein, and a control method thereof.